MIME-Version: 1.0 Received: from AM4PR07MB1298.eurprd07.prod.outlook.com (10.164.81.156) by DB5PR07MB1301.eurprd07.prod.outlook.com (10.164.41.155) with Microsoft SMTP Server (TLS) id 15.1.274.16 via Mailbox Transport; Sun, 20 Sep 2015 17:02:31 +0000 Authentication-Results: linutronix.de; dkim=none (message not signed) header.d=none;linutronix.de; dmarc=none action=none header.from=numascale.com; Received: from localhost.localdomain (175.156.157.249) by AM4PR07MB1298.eurprd07.prod.outlook.com (10.164.81.156) with Microsoft SMTP Server (TLS) id 15.1.274.16; Sun, 20 Sep 2015 17:02:27 +0000 From: Daniel J Blueman To: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" CC: Daniel J Blueman , , , Daniel Lezcano , Steffen Persvold Subject: [PATCH 4/4] x86: Introduce Numachip2 timer mechanisms Date: Mon, 21 Sep 2015 01:02:02 +0800 Message-ID: <1442768522-19217-4-git-send-email-daniel@numascale.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1442768522-19217-1-git-send-email-daniel@numascale.com> References: <1442768522-19217-1-git-send-email-daniel@numascale.com> Content-Type: text/plain X-MS-Exchange-Organization-Network-Message-Id: cf558fcb-4e09-4178-3d8f-08d2c1dd454b X-MS-Exchange-Organization-AuthSource: AM4PR07MB1298.eurprd07.prod.outlook.com X-MS-Exchange-Organization-AuthAs: Internal X-MS-Exchange-Organization-AuthMechanism: 06 X-Originating-IP: [175.156.157.249] X-ClientProxiedBy: DB5PR03CA0064.eurprd03.prod.outlook.com (25.164.34.32) To AM4PR07MB1298.eurprd07.prod.outlook.com (25.164.81.156) Return-Path: daniel@numascale.com X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1298;2:/hsThpn4fd7vzRT3pkN0HGgWSWpvpBylFVDmehnWRnYZpljh8aDW1YWljDJWWzaM7VMeTgHMtyHNRAygwYNCGiSFdf3aZ1o2lzJawl+Ua3rFWLI8BKo2U+1pQrV+klkE8bWCBIE8eH6pPgFEyjoIfzHnW3V7VAc3Lx4STwl5ce8=;3:fuDHXxycFTvJl8SY4W6b7tIUuyNRrB74yp+DDkuwfLIc9nbuRddgtTCGI/XWHw0IyaSRuQgVtG4aBZfArJDYm63aKFZdWtsdZb9zKfu9Jl2ytzIExoBkuIGSKwk+GBPa99woMajL5dLswDI34WgdrA==;25:PVJKK1QISvYXMsLfIU/geY9qAFMgD/BT1FylCxXiUZp8bzmsg3VP5pT0EHfkGAi4GkVx6SwfTlH7IUe1RJG3KDti1zlVLwMwlY7rFvrTd4mpz+aumNKaPAeOHr2ajxPHygZkARpPxLN99q72ulANkPg72Jc7dWAOpz3KPFdCIM0n9X76NWo/3a4XzE5NgH5FF1vjQlSc0wsdRYDzo2r/DtTYeYufeeod1/xgPOKUgTX3Ew3Wlfi+RmwOyyi/PgFh;4:Yhy8ul2xfILOrbV39pOgYPri0tsI8ohb9y3mBLF+Tfq0RpaaSKAOmQM0AwLs/En28xTbIQ2J3p1iNKhLH/J+1GgOW3PoJHwBm7UOjdk5ARF4sWflUI+LPjDJFVC2AzHfmc68FZfKofOPE2LQIgHhdwT9qVh7vA0ADSxYTbe87h8PSpdsk7z4meKIhAApWFDwXS5XEM3NEEuYyFJgyi40WFcW+dN1AogMhSuBzkHRL2g= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298; X-MS-Exchange-Organization-AVStamp-Service: 1.0 X-Exchange-Antispam-Report-CFA: BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298; X-Forefront-Antispam-Report: SFV:SKI;SFS:;DIR:INB;SFP:;SCL:-1;SRVR:AM4PR07MB1298;H:localhost.localdomain;FPR:;SPF:None;LANG:en; X-MS-Exchange-Organization-SCL: -1 X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1298;23:8TvaL0UElzsZrEFGKeRvdCWevhivf+GdOxsse4/Tu8Z/ofNRU1Wo7rIb/b69fqpwXthzUBL8uXj0tHA345gD3q//AvjMtirPwUqHOSI2xOWRvhJ68PvOsGIg5SthANn9e1u/gq86AXFiv3V7bxCOfvlpkCx/PfLe4LKZWuyq877g9jS3faoSh+uGnYSFMmZY;5:IkJ64pSsnoeEF67cffroqV/FoIG/dDtSdL5BnbgFQtxJCS1qmzDSTr+nKs995yTKFp2yzDmFabMeYlTdIYnsTfhZLzWHK92lmHEDjSfLHufsMRZAj/OCC5Vez/zVxmAbUbabsCigl+ocq3FNg78kaQ==;24:l0gBTLWKSeueenVXroviF3szpFohW123o0Qalcpif0oOVOEvaCbZRepwU43f9NOx+MQ25YEjFHfNuRoV6GshiybT7Tk50n+hTbIPIEsApCQ=;20:nDn3LGdbwDj5wPJSrWRHAnrawrJBxQOz2lnbq4znkei9Rqfs1lDkVQxh5ysTND3nKr6qnaDVL4v9788Qoyx5uQ== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2015 17:02:27.9652 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR07MB1298 X-MS-Exchange-Organization-MessageDirectionality: Originating X-MS-Exchange-Transport-EndToEndLatency: 00:00:03.5147439 Add 1GHz 64-bit Numachip2 clocksource timer support for accurate system-wide timekeeping, as core TSCs are unsynchronised. Additionally, add a per-core clockevent mechanism that interrupts via the platform IPI vector after a programmed period. Signed-off-by: Daniel J Blueman Acked-by: Steffen Persvold --- arch/x86/include/asm/numachip/numachip_csr.h | 9 +++++++++ drivers/clocksource/Makefile | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/numachip/numachip_csr.h b/arch/x86/include/asm/numachip/numachip_csr.h index e09d845..29719ee 100644 --- a/arch/x86/include/asm/numachip/numachip_csr.h +++ b/arch/x86/include/asm/numachip/numachip_csr.h @@ -59,6 +59,10 @@ static inline void write_lcsr(unsigned long offset, unsigned int val) #define NUMACHIP2_LCSR_BASE 0xf0000000UL #define NUMACHIP2_LCSR_SIZE 0x1000000UL #define NUMACHIP2_APIC_ICR 0x100000 +#define NUMACHIP2_TIMER_DEADLINE 0x200000 +#define NUMACHIP2_TIMER_INT 0x200008 +#define NUMACHIP2_TIMER_NOW 0x200018 +#define NUMACHIP2_TIMER_RESET 0x200020 static inline void __iomem *numachip2_lcsr_address(unsigned long offset) { @@ -86,4 +90,9 @@ static inline void numachip2_write64_lcsr(unsigned long offset, u64 val) writeq(val, numachip2_lcsr_address(offset)); } +static inline unsigned int numachip2_timer(void) +{ + return (smp_processor_id() % 48) << 6; +} + #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */ diff --git a/drivers/clocksource/numachip.c b/drivers/clocksource/numachip.c new file mode 100644 index 0000000..5e4f90e --- /dev/null +++ b/drivers/clocksource/numachip.c @@ -0,0 +1,95 @@ +/* + * + * Copyright (C) 2015 Numascale AS. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include + +static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); + +static cycles_t numachip2_timer_read(struct clocksource *cs) +{ + return numachip2_read64_lcsr(NUMACHIP2_TIMER_NOW); +} + +static struct clocksource numachip2_clocksource = { + .name = "numachip2", + .rating = 295, + .read = numachip2_timer_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .mult = 1, + .shift = 0, +}; + +static int numachip2_set_next_event(unsigned long delta, struct clock_event_device *ced) +{ + numachip2_write64_lcsr(NUMACHIP2_TIMER_DEADLINE + numachip2_timer(), + delta); + return 0; +} + +static struct clock_event_device numachip2_clockevent = { + .name = "numachip2", + .rating = 400, + .set_next_event = numachip2_set_next_event, + .features = CLOCK_EVT_FEAT_ONESHOT, + .mult = 1, + .shift = 0, + .min_delta_ns = 1250, + .max_delta_ns = LONG_MAX, +}; + +static void numachip_timer_interrupt(void) +{ + struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); + + ced->event_handler(ced); +} + +static __init void numachip_timer_each(struct work_struct *work) +{ + unsigned local_apicid = __this_cpu_read(x86_cpu_to_apicid) & 0xff; + struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); + + /* Setup IPI vector to local core and relative timing mode */ + numachip2_write64_lcsr(NUMACHIP2_TIMER_INT + numachip2_timer(), + (3 << 22) | (X86_PLATFORM_IPI_VECTOR << 14) | + (local_apicid << 6)); + + *ced = numachip2_clockevent; + ced->cpumask = cpumask_of(smp_processor_id()); + clockevents_register_device(ced); +} + +static int __init numachip_timer_init(void) +{ + if (numachip_system != 2) + return -ENODEV; + + /* Reset timer */ + numachip2_write64_lcsr(NUMACHIP2_TIMER_RESET, 0); + clocksource_register_hz(&numachip2_clocksource, NSEC_PER_SEC); + + /* Setup per-cpu clockevents */ + x86_platform_ipi_callback = numachip_timer_interrupt; + schedule_on_each_cpu(&numachip_timer_each); + + return 0; +} + +arch_initcall(numachip_timer_init); -- 2.5.0 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index f228354..6ca3c92 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o obj-$(CONFIG_H8300) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o +obj-$(CONFIG_X86_NUMACHIP) += numachip.o