MIME-Version: 1.0 Received: from AM4PR07MB1298.eurprd07.prod.outlook.com (10.164.81.156) by DB5PR07MB1301.eurprd07.prod.outlook.com (10.164.41.155) with Microsoft SMTP Server (TLS) id 15.1.274.16 via Mailbox Transport; Sun, 20 Sep 2015 17:02:24 +0000 Authentication-Results: linutronix.de; dkim=none (message not signed) header.d=none;linutronix.de; dmarc=none action=none header.from=numascale.com; Received: from localhost.localdomain (175.156.157.249) by AM4PR07MB1298.eurprd07.prod.outlook.com (10.164.81.156) with Microsoft SMTP Server (TLS) id 15.1.274.16; Sun, 20 Sep 2015 17:02:21 +0000 From: Daniel J Blueman To: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" CC: Daniel J Blueman , , , Daniel Lezcano , Steffen Persvold Subject: [PATCH 2/4] x86: Add Numachip2 APIC support Date: Mon, 21 Sep 2015 01:02:00 +0800 Message-ID: <1442768522-19217-2-git-send-email-daniel@numascale.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1442768522-19217-1-git-send-email-daniel@numascale.com> References: <1442768522-19217-1-git-send-email-daniel@numascale.com> Content-Type: text/plain X-MS-Exchange-Organization-Network-Message-Id: c7669b93-dbe0-433f-297f-08d2c1dd4151 X-MS-Exchange-Organization-AuthSource: AM4PR07MB1298.eurprd07.prod.outlook.com X-MS-Exchange-Organization-AuthAs: Internal X-MS-Exchange-Organization-AuthMechanism: 06 X-Originating-IP: [175.156.157.249] X-ClientProxiedBy: DB5PR03CA0064.eurprd03.prod.outlook.com (25.164.34.32) To AM4PR07MB1298.eurprd07.prod.outlook.com (25.164.81.156) Return-Path: daniel@numascale.com X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1298;2:MP4/YZDZ+66trvWIX7yJCnZar4DEthOCN1Ph2+xl+qNSnSQag/1/gSsdwnWVcJIZ9IqOCkbGzMQBzPaDrlmc7526z5q9ztQWmP7HW9u/2GAk17a/uf2WJrVsTlq1vgwfHUpYLVH3skzUjifAFaurhiYWHHUsKj8sABKdjU5+M5c=;3:rdwEcRzYIiwzDpGv45/ypYFghrz4Aps6yClQT0o2rhbxjpOGQKEY85v0LovFtCbb5juMeyjd5NuvJI9qiOU47M2Rmiink6crB3k4maY8DZhvlw7SqbXLmn8RkfC34IFzp+OwfI4ILA/ja2CDMc9zsg==;25:vQ7EpLeApj9BUdW0IybXKKqLEnTEB8lyuR6IQAMR///SIO2utu0+eLJ8cyaQxPA6qykbsfXN7/xICW4IS+HCm14DefSlw1btIXpoKZuJYu43GYh7I/0f/XRNoqGkxHVg368ghEGVzfxzev6kjSmHnpjFv/wYqlVx+3O3Z0+fee2hsovq2c4deopr+6QHJA2Fj9EiZOn+VNJ5N9GFJAKnljE59P5yA3BWn6kt5Nk1CWHlthsEBp7MbXA+0CrAT3oK;4:vuR8mFaye0QKzlmpLsmRM+flG9LNnc4WI/NBRi3CCY/8FeP8OBCe8wUtLdfTa1rdTHR77eWUsXmm1aL/VvITCRdqhet9gdykQeutTRAhboFluBy1M6zpqW10mXkJHnyLdtVB1Ryp5P+22xYasBu7XdpdN4Ix6Fn75vWqPBgDMvwPYm/v+KQKA4klqq1azRy8XBT1LFng5YlIe2zoHgPGEOxjZb7DI8lDFpX/BMGj604= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298; X-MS-Exchange-Organization-AVStamp-Service: 1.0 X-Exchange-Antispam-Report-CFA: BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1298; X-Forefront-Antispam-Report: SFV:SKI;SFS:;DIR:INB;SFP:;SCL:-1;SRVR:AM4PR07MB1298;H:localhost.localdomain;FPR:;SPF:None;LANG:en; X-MS-Exchange-Organization-SCL: -1 X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1298;23:zXJ/7vAcfQSsftu4lle1PQb6J63M/p8ykqOsfrzEoaA74fX9ZoPGCE7mhvAlNO8izaSgeSKY7aLRbMyEUI4U0eCkc8+rDZ0DKLzd6TytUwOqi+VvNeQazZJVMQD7brGQkwksHJVXtPheC9Gy/ppbiKZcm9VPX0N1X0r+ltv6cIizjfwAu0zKnoewY/W/iWHg;5:45PoytYYiYPSkPPGR9lPJFGJ19epEGERehzyFQAwpViKt0dh7PrsxOCFIWG+EAfLby5PxNEIy6ROT3fc1gFPdujLrGUSIn5i+fivvoFm3leeCF0Z5KGnW8HFF+WSJNiWhQ67V9IZo9x3UxznLaDd+w==;24:v5vyawgZOUzUYOhAt2F7M2EU8B7jTYV0OXc64YrZSsVHQ0BH2jcwNRfaf+KZStJZS+mrAp/XGlCTSr0QRa/8Qv4zhiOZf5jwXtyxHK4A7Rk=;20:Y5AKIhpJRcWFO2YmhK9Ww0slMg+3gBOXh9lU4/TPJYdvZW9N3ytu7kOVggM4PNr9bB5ZHHQPsnjKPXc4jcD6TA== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2015 17:02:21.2931 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR07MB1298 X-MS-Exchange-Organization-MessageDirectionality: Originating X-MS-Exchange-Transport-EndToEndLatency: 00:00:03.6084697 Introduce support for Numachip2 remote interrupts via detecting the right ACPI SRAT signature. Access is performed via a fixed mapping in the x86 physical address space. Signed-off-by: Daniel J Blueman Acked-by: Steffen Persvold --- arch/x86/include/asm/numachip/numachip.h | 1 + arch/x86/include/asm/numachip/numachip_csr.h | 34 ++++++++++ arch/x86/kernel/apic/apic_numachip.c | 93 ++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) diff --git a/arch/x86/include/asm/numachip/numachip.h b/arch/x86/include/asm/numachip/numachip.h index 1c6f7f6..c64373a 100644 --- a/arch/x86/include/asm/numachip/numachip.h +++ b/arch/x86/include/asm/numachip/numachip.h @@ -14,6 +14,7 @@ #ifndef _ASM_X86_NUMACHIP_NUMACHIP_H #define _ASM_X86_NUMACHIP_NUMACHIP_H +extern u8 numachip_system; extern int __init pci_numachip_init(void); #endif /* _ASM_X86_NUMACHIP_NUMACHIP_H */ diff --git a/arch/x86/include/asm/numachip/numachip_csr.h b/arch/x86/include/asm/numachip/numachip_csr.h index 7469b13..c7efc25 100644 --- a/arch/x86/include/asm/numachip/numachip_csr.h +++ b/arch/x86/include/asm/numachip/numachip_csr.h @@ -14,6 +14,7 @@ #ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H #define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H +#include #include #define CSR_NODE_SHIFT 16 @@ -50,4 +51,38 @@ static inline void write_lcsr(unsigned long offset, unsigned int val) writel(swab32(val), lcsr_address(offset)); } +/* + * On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G + */ + +#define NUMACHIP2_LCSR_BASE 0xf0000000UL +#define NUMACHIP2_LCSR_SIZE 0x1000000UL +#define NUMACHIP2_APIC_ICR 0x100000 + +static inline void __iomem *numachip2_lcsr_address(unsigned long offset) +{ + return (void __iomem *)__va(NUMACHIP2_LCSR_BASE | + (offset & (NUMACHIP2_LCSR_SIZE - 1))); +} + +static inline u32 numachip2_read32_lcsr(unsigned long offset) +{ + return readl(numachip2_lcsr_address(offset)); +} + +static inline u64 numachip2_read64_lcsr(unsigned long offset) +{ + return readq(numachip2_lcsr_address(offset)); +} + +static inline void numachip2_write32_lcsr(unsigned long offset, u32 val) +{ + writel(val, numachip2_lcsr_address(offset)); +} + +static inline void numachip2_write64_lcsr(unsigned long offset, u64 val) +{ + writeq(val, numachip2_lcsr_address(offset)); +} + #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */ diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c index 8729249..dfe2b1c 100644 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -22,6 +22,7 @@ u8 numachip_system __read_mostly; static const struct apic apic_numachip1; +static const struct apic apic_numachip2; static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly; static unsigned int numachip1_get_apic_id(unsigned long x) @@ -45,6 +46,19 @@ static unsigned long numachip1_set_apic_id(unsigned int id) return x; } +static unsigned int numachip2_get_apic_id(unsigned long x) +{ + u64 mcfg; + + rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg); + return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); +} + +static unsigned long numachip2_set_apic_id(unsigned int id) +{ + return id << 24; +} + static int numachip_apic_id_valid(int apicid) { /* Trust what bootloader passes in MADT */ @@ -66,6 +80,11 @@ static void numachip1_apic_icr_write(int apicid, unsigned int val) write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); } +static void numachip2_apic_icr_write(int apicid, unsigned int val) +{ + numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val); +} + static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) { numachip_apic_icr_write(phys_apicid, APIC_DM_INIT); @@ -129,6 +148,11 @@ static int __init numachip1_probe(void) return apic == &apic_numachip1; } +static int __init numachip2_probe(void) +{ + return apic == &apic_numachip2; +} + static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) { u64 val; @@ -154,6 +178,13 @@ static int __init numachip_system_init(void) numachip_apic_icr_write = numachip1_apic_icr_write; x86_init.pci.arch_init = pci_numachip_init; break; + case 2: + init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE); + numachip_apic_icr_write = numachip2_apic_icr_write; + + /* Use MCFG config cycles rather than locked CF8 cycles */ + raw_pci_ops = &pci_mmcfg; + break; default: return 0; } @@ -175,6 +206,17 @@ static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id) return 1; } +static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id) +{ + if ((strncmp(oem_id, "NUMASC", 6) != 0) || + (strncmp(oem_table_id, "NCONECT2", 8) != 0)) + return 0; + + numachip_system = 2; + + return 1; +} + static const struct apic apic_numachip1 __refconst = { .name = "NumaConnect system", .probe = numachip1_probe, @@ -225,3 +267,54 @@ static const struct apic apic_numachip1 __refconst = { }; apic_driver(apic_numachip1); + +static const struct apic apic_numachip2 __refconst = { + .name = "NumaConnect2 system", + .probe = numachip2_probe, + .acpi_madt_oem_check = numachip2_acpi_madt_oem_check, + .apic_id_valid = numachip_apic_id_valid, + .apic_id_registered = numachip_apic_id_registered, + + .irq_delivery_mode = dest_Fixed, + .irq_dest_mode = 0, /* physical */ + + .target_cpus = online_target_cpus, + .disable_esr = 0, + .dest_logical = 0, + .check_apicid_used = NULL, + + .vector_allocation_domain = default_vector_allocation_domain, + .init_apic_ldr = flat_init_apic_ldr, + + .ioapic_phys_id_map = NULL, + .setup_apic_routing = NULL, + .cpu_present_to_apicid = default_cpu_present_to_apicid, + .apicid_to_cpu_present = NULL, + .check_phys_apicid_present = default_check_phys_apicid_present, + .phys_pkg_id = numachip_phys_pkg_id, + + .get_apic_id = numachip2_get_apic_id, + .set_apic_id = numachip2_set_apic_id, + .apic_id_mask = 0xffU << 24, + + .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, + + .send_IPI_mask = numachip_send_IPI_mask, + .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, + .send_IPI_allbutself = numachip_send_IPI_allbutself, + .send_IPI_all = numachip_send_IPI_all, + .send_IPI_self = numachip_send_IPI_self, + + .wakeup_secondary_cpu = numachip_wakeup_secondary, + .inquire_remote_apic = NULL, /* REMRD not supported */ + + .read = native_apic_mem_read, + .write = native_apic_mem_write, + .eoi_write = native_apic_mem_write, + .icr_read = native_apic_icr_read, + .icr_write = native_apic_icr_write, + .wait_icr_idle = native_apic_wait_icr_idle, + .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, +}; + +apic_driver(apic_numachip2); -- 2.5.0